Process Engineering and Defect Prevention

Article originally published in The PCB Magazine.

As of this writing, I have explored many topics related to specific defects that plague printed circuit board fabricators. A key under- lying theme of these writings underscores the critical need of the skilled troubleshooter to get to the underlying cause or causes of the defects. Defects may “manifest” or be detected in or after a specific operation within the printed circuit board manufacturing process, but the underlying root cause may have occurred earlier (perhaps much earlier) in the process. As I have written in prior columns, I chose to present the anomaly or defect where it is most likely to be detected, then subsequently presented the most likely root causes wherever they might have been introduced. It should be noted that these examples are presented as likely starting places for the investigation of anomalies or defects presented, or the kinds of causes that might be investigated.

The troubleshooter’s task is  complicated  by the fact that there are many possible ways  to combine or sequence the individual process steps available to achieve the desired end structure. As an example, a simple, single-lamination multilayer printed wiring board may involve 30 to 50 process steps, while a complex, multiple lamination (sequential lamination) printed wiring board, with pre- and post-machining and other mechanical operations, and selective plating processes, could involve several hundred process steps. In an ideal world, each step could  be verified correct immediately during or after the process, but in practice the effect of many processes cannot be readily evaluated until the completion of many subsequent steps make latent errors visible. Much effort is and has been expended in attempts to improve this, with limited success. Thus, it remains a troublesome issue. The concern then is the defect may not manifest itself until several downstream process steps. One may refer to this as the latent defect. The impact of these latent defects is four-fold:

  1. First, the detection and verification of the defect may require real time and the diversion of skilled resources—already in short supply in most lean-running modern
  2. Second, there is a schedule  impact  in today’s just-in-time operating mode, both of the process flow disruption inherent in the detection and in the verification of the defect. Far more important is the double impact of the wasted process time and effort invested to the point of detection, and the necessity of repeating that processing. The combined schedule disruption will cascade through the producer, the immediate customer, all the way to end-customer’s delivery/implementation commitments.
  3. Third, the cost impact of the lost labor and materials, possibly compounded by expediting costs (overtime and raw material rush replacement premiums).
  4. Fourth, lost opportunities for other valuable or urgent work that cannot be accomplished while resources and materials are diverted to the recovery.

More complex printed circuit board structures may require multiple “loops”  through the process from multilayer layup through tin strip, and selective plating increases the number of loops through the imaging and plating sequences. These have the obvious effect of in- creasing the required process time, but also the less-obvious effect of increased risk of yield loss. The message here: Process engineering adjustments and close attention to detail are needed. Various simulation models of cumulative ef- fect of process complexity on yield have been put forward (including some which pessimistically predict that no printed board of sufficient complexity can (mathematically) ever be successfully produced). While the picture is not quite that bleak, it is clear that complexity adds to cost, build time, and risk of loss (with the resultant schedule impact). To the extent possible, additional early effort expended in simplifying a design, or its build process will yield benefits in the long run.

Process Design and Control

With  increasing  circuit  board  complexity comes the greater possibility of defects. A surprisingly common underlying cause of defects, particularly in high-mix/low-volume operations (characteristically, quick-turn, prototype, specialty production, etc.), where frequent changeovers between products produced is experienced, is incorrect (or sub-optimal) conversion of the incoming data and requirements into the working process sequence and/or test and measurement requirements. The wide variety of work types and configurations processed in such operations may delay recognition that an error has, in fact, occurred until it is too late to salvage the product.

Common errors include (in no order of criticality):

  • Omission or transposition of selective plating or etching mask areas from data package to production working phototools
  • Skipped, or mis-ordered process steps
  • Data collection instructions omitted for a specific process step not readily retrieved later, or necessary test vehicles (coupons) not added to the initial panelization scheme
  • Premature removal of electroplating buss-bars (electrical tie-in), in-process test points, or of etch-resist metallization
  • Transposed (or just incorrect) dimensions incorporated into mechanical operation programming (drilling, milling), especially when manual or override is required by the data

Process control excursions (or process break- downs) that are undetected until after an operation remain as hurdles to high-yield, flexible-response manufacturing. Scrap (or suspect product) containment is a major focus at high-speed, high-volume processes, particularly continuous (reel-to-reel, automotive, or cellular production, for example) processes. Automatic monitoring and shutdown (or at least alarm) of key process parameters is becoming the norm. Process control and process monitoring are key levers that one can pull to insure process repeatability and performance consistency. However, process engineering improvements often overlook process conditions such as rinse water temperature and cleanliness, pH controls, rectifier issues that reduce electroplating quality, malfunctioning temperature controllers, etc. These are just a few of the potential process engineering issues that if not corrected, will contribute to printed board defects and loss of revenue. Learning that some very expensive printed circuit boards are found to fail in the field due to lack of process engineering or lack of simple controls is both devastating financially as well as compromising confidence of the customer. Let’s look at some real-world examples where several different root cause issues lead to the “observed defect”  or non-conformance.


Most process problems that appear during the etching stage of printed circuit production can be traced to one of two general areas. The most obvious causes (though not necessarily the most common) of etching problems occur in the etching equipment itself, either through equipment failure or mis-adjustment or chemistry outside normal operating parameters. As is often the case in printed circuit processing, anomalies detected during or after the etching step may trace back to technical issues induced during prior processing steps but not detected until the boards are processed through the etcher. An example would be resist scum left on the board during the stripping of a plating resist, which can cause uneven etching to occur, although blocked nozzles, “tracking” from rollers, uneven distribution (top to bottom, or across the machine) of spray pressure can all mimic the effects of incomplete resist removal under some circumstances.

Figure 1 shows what appears as unetched copper. The excess remaining copper will lead to either a short or at the very least violate the spacing requirements. The possible causes for this defect as well as likely solutions are listed in the Table 1.

Figure 2 depicts a circuit trace that has been etched out and is very close to having an open created. It would be easiest to point the finger at the etching operation. However, the skilled troubleshooter will not fall into that trap.

The engineer should note that the defect is not widespread. The issue is isolated to a few spots. While it would be easiest to blame the etching operation, experienced process engineers would look elsewhere first. A few of the most likely causes and solutions are shown in Table 2.

While there are many more possible defects related or at least attributable to etching, this column is not meant to address them all. In addition, one needs to review defects that manifest themselves in the plated through- hole  (i.e., electroplating).



Electroplating in the manufacture of print- ed wiring is used to deposit a metallic pattern, generally on copper-clad substrates. Plating acceptability is judged by plating thickness, adhesion, ductility and uniformity (the presence of inclusions, nodules, voids or cracks). Factors that affect these criteria are board surface preparation, board racking and  handling, control of chemical parameters, and physical parameters of the plating operation (solution filtration, distribution, anode/cathode placement  and geometry, etc.).

Some of these variables are capable of “immediate” control by the operator (adjustment of plating chemistry, temperatures, etc.) and others can be changed only slightly, or with difficulty such as varying the geometry of an- ode/cathode placement. This adjustment is limited by the geometry of the plating line and individual tanks as installed.

One of the very troublesome defects is corner cracking in the electroplated copper with- in the PTH (Figure 3). The potential root causes and solutions are listed in Table 3.

This real-life example underscores the need to have a deep understanding of how variations in one or more processes may cause the defect several steps removed. One can surmise that the processes or processes need improved controls as well as more sophisticated analytical methods. In addition, regular tensile and elongation measurements will serve as a leading indicator for possible copper cracking.

Finally, in Figure 4, the classic innerplane separation is observed. At first glance, it may be easy to determine that the root cause of the separation is that the electroless copper deposit separated from the innerlayer post. That is certainly a logical conclusion. And one is viewing the section after solder excursion and without etching the specimen (which is correct procedure up to this point). However, further study is required.

Is that separation due to some resin smear remaining on the post? Thus, preventing the adhesion of the electroless copper to the post? And whether the separation is due to resin smear or simply the copper separating, it is nonetheless a separation and a non-conforming defect. Regardless, the unetched specimen shows a separation. However, where does one go from here to troubleshoot the problem? Clearly there is no evidence of any etchback so it is possible there is drill smear remaining. It is somewhat difficult at this point to detect smear without SEM/EDAX. The skilled troubleshooter will now accept the challenge of reviewing whether this defect is more widespread or an isolated case. Table 4 lists several possible causes for the defect seen in Figure 4.

Troubleshooting defects and process issues starts first with optimizing the processes for highest yields possible. However, even the best engineering does not guarantee the total elimination of defects in the process-intense PCB manufacturing process.

Thus, the good troubleshooter enhances the problem-solving exercise using various Six Sigma techniques. The one used here by the author and illustrated throughout this article is the DMAIC method:

  • Define the problem and goal, identify the customers served by the process, and define customer requirements
  • Measure—refine the problem statement, decide what to measure, and begin the search for root causes
  • Analyze the data looking for trends, patterns, etc.
  • Improve—develop innovative new processes
  • Control—institute controls to insure improvements remain. Document all activities for future usage/training

There was quite a lot of subject matter here. However, it should be recognized that noting can substitute for a methodical approach to problem solving utilizing all the tools and knowledge available to the troubleshooter.

Figure 1: Excess or unetched copper. (Source: IPC photo archive, Bannockburn, Illinois)

Figure 2: Nearly etched-out circuit trace. (Source: RBP Chemical Technology)

Figure 3: Electroplated copper cracks after thermal excursion. (Source: RBP Chemical Technology)

Figure 4: Separation of plated copper from the innerlayer post. (Source: IPC photo archive, Bannockburn, Illinois)

Originally published in The PCB Magazine.

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